Self-encapsulated copper metallization

ABSTRACT

Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.

TECHNICAL FIELD

The present invention relates to electroplated or electroless platedcopper or copper alloy metallization. The present invention isapplicable to manufacturing high speed integrated circuits havingsubmicron design features and high conductivity interconnect structures.

BACKGROUND ART

The escalating requirements for high density and performance associatedwith ultra large scale integration semiconductor wiring requireresponsive changes in interconnection technology, which is consideredone of the most demanding aspects of ultra large scale integrationtechnology. Such escalating requirements have been found difficult tosatisfy in terms of providing a low RC (resistance capacitance)interconnect pattern, particularly wherein submicron vias, contacts andtrenches have high aspect ratios due to miniaturization.

Conventional semiconductor devices comprise a semiconductor substrate,typically doped monocrystalline silicon, and a plurality of sequentiallyformed dielectric interlayers and conductive patterns. An integratedcircuit is formed containing a plurality of conductive patternscomprising conductive lines separated by interwiring spacings, and aplurality of interconnect lines, such as bus lines, bit lines, wordlines and logic interconnect lines. Typically, the conductive patternson different layers, i.e., upper and lower layers, are electricallyconnected by a conductive plug filling a via hole, while a conductiveplug filling a contact hole establishes electrical contact with anactive region on a semiconductor substrate, such as a source/drainregion. Conductive lines formed in trench openings typically extendsubstantially horizontal with respect to the semiconductor substrate.Semiconductor “chips” comprising five or more levels of metallizationare becoming more prevalent as device geometries shrink to submicronlevels.

A conductive plug filling a via hole is typically formed by depositing adielectric interlayer on a conductive layer comprising at least oneconductive pattern, forming an opening through the dielectric interlayerby conventional photolithographic and etching techniques, and fillingthe opening with a conductive material, such as tungsten (W). Excessconductive material on the surface of the dielectric interlayer istypically removed by chemical-mechanical polishing (CMP) One such methodis known as damascene and basically involves the formation of an openingwhich is filled in with a metal. Dual damascene techniques involve theformation of an opening comprising a lower contact or via hole sectionin communication with an upper trench section, which opening is filledwith a conductive material, typically a metal, to simultaneously form aconductive plug in electrical contact with a conductive line. Incopending application Ser. No. 08/320,516 filed on Oct. 11, 1994, priorart single and dual damascene techniques are disclosed, in addition toseveral improved dual damascene techniques simultaneously forming aconductive line in electrical contact with a conductive plug for greateraccuracy in forming fine line patterns with minimal interwiringspacings.

High performance microprocessor applications require rapid speed ofsemiconductor circuitry. The control speed of semiconductor circuitryvaries inversely with the resistance and capacitance of theinterconnection pattern. As integrated circuits become more complex andfeature sizes and spacings become smaller, the integrated circuit speedbecomes less dependent upon the transistor itself and more dependentupon the interconnection pattern. Thus, the interconnection patternlimits the speed of the integrated circuit.

If the interconnection node is routed over a considerable distance,e.g., hundreds of microns or more, as in submicron technologies, theinterconnection capacitance limits the circuit node capacitance loadingand, hence, the circuit speed. As integration density increases andfeature size decreases in accordance with submicron design rules, therejection rate due to integrated circuit speed delays approaches andeven exceeds 20%.

One way to increase the control speed of semiconductor circuitry is toreduce the resistance of a conductive pattern. Conventionalmetallization patterns are typically formed by depositing a layer ofconductive material, notably aluminum (Al) or an alloy thereof, andetching, or by damascene techniques wherein trenches are formed indielectric layers and filled with a conductive material. Excessconductive material on the surface of the dielectric layer is thenremoved by CMP. Al is conventionally employed because it is relativelyinexpensive, exhibits low resistivity and is relatively easy to etch.However, as the size of openings for vias/contacts and trenches isscaled down to the sub-micron range, step coverage problems have ariseninvolving the use of Al which has decreased the reliability ofinterconnections formed between different wiring layers. Such poor stepcoverage results in high current density and enhanced electromigration.Moreover, low dielectric constant polyamide materials, when employed asdielectric interlayers, create moisture/bias reliability problems whenin contact with Al.

One approach to improved interconnection paths in vias comprises the useof completely filled plugs of a metal, such as W. Accordingly, manycurrent semiconductor devices utilizing VLSI (very large scaleintegration) technology employ Al for a wiring metal and W plugs forinterconnections at different levels. However, the use W is attendantwith several disadvantages. For example, most W processes are complexand expensive. Moreover, W has a high resistivity. The Joule heating mayenhance electromigration of adjacent Al wiring. Furthermore, W plugs aresusceptible to void formation and the interface with the wiring layerusually results in high contact resistance.

Another attempted solution for the Al plug interconnect problemcomprises the use of chemical vapor deposition (CVD) or physical vapordeposition (PVD) at elevated temperatures for Al deposition. The use ofCVD for depositing Al has proven expensive, while hot PVD Al depositionrequires very high process temperatures incompatible with manufacturingintegrated circuitry.

Copper (Cu) and Cu alloys have received considerable attention as acandidate for replacing Al in VLSI interconnect metallizations. Cuexhibits superior electromigration properties and has a lowerresistivity than Al. In addition, Cu has improved electrical propertiesvis-á-vis W, making Cu a desirable metal for use as a conductive plug aswell as conductive wiring.

Electroless plating and electroplating of Cu and Cu alloys offer theprospect of low cost, high throughput, high quality plated films andefficient via, contact and trench filling capabilities. Electrolessplating generally involves the controlled autocatalytic deposition of acontinuous film on the catalytic surface by the interaction in solutionof a metal salt and a chemical reducing agent. Electroplating comprisesthe electro deposition of an adherent metallic coating on an electrodeemploying externally supplied electrons to reduce metal ions in theplating solution. A seed layer is required to catalyze electrolessdeposition or to carry electrical current for electroplating. Forelectroplating, the seed layer must be continuous. For electrolessplating, very thin catalytic layers, e.g., less than 100 Å, can beemployed in the form of islets of catalytic metal.

There are disadvantages attendant upon the use of Cu or Cu alloys. Forexample, Cu is easily oxidized and vulnerable to corrosion. Unlike Al,Cu does not form a self-passivating oxide on its surface. Accordingly,corrosion of Cu is an important issue which requires resolution beforeCu can be effectively utilized in many semiconductor deviceapplications. Moreover, Cu readily diffuses through silicon dioxide, thetypical dielectric interlayer material employed in the manufacture ofsemiconductor devices, into silicon elements and adversely affectsdevice performance.

One approach to forming Cu plugs and wiring comprises the use ofdamascene structures employing CMP, as in Chow et al., U.S. Pat. No.4,789,648. However, due to Cu diffusion through dielectric interlayermaterials, such as silicon dioxide, Cu interconnect structures must beencapsulated by a diffusion barrier layer. Typical diffusion barriermetals include tantalum (Ta) , tantalum nitride (TaN), titanium nitride(TiN), titanium-tungsten (TiW), and silicon nitride (Si₃N₄) forencapsulating Cu. The use of such barrier materials to encapsulate Cu isnot limited to the interface between Cu and the dielectric interlayer,but includes interfaces with other metals as well.

In copending application Ser. No. 08/857,129, filed May 15, 1997, nowU.S. Pat. No. 5,969,422, issued Oct. 19, 1999 a method of electrolessplating or electroplating copper or a copper alloy to fill high aspectratio openings is disclosed, wherein a seed layer comprising an alloy ofa refractory metal and one or more additive metals is initiallydeposited.

Copending application Ser. No. 08/587,264, filed Jan. 16, 1996,discloses a method of electrolessly depositing Cu in an interconnectstructure, which method comprises initially depositing a barrier layerin an opening, depositing a catalytic seed layer, preferably of Cu, onthe barrier layer, and then depositing a protective layer the catalyticlayer encapsulating and protecting the catalytic layer from oxidation.The preferred protective material is Al which forms an Al—Cu alloy atthe interface of the catalytic and protective layers, therebyencapsulating the underlying Cu. Subsequently, Cu is electrolesslydeposited from an electroless deposition solution which dissolves theoverlying protective alloy layer to expose the underlying catalytic Culayer.

Al has been suggested as a doping material to improve the oxidation andcorrosion resistance of Cu and act as a diffusion barrier by forming athin protective layer of aluminum oxide on the surface of a Cu layerupon annealing. P. J. Ding et al., “Effects of the Addition of SmallAmounts of Al to Copper: Corrosion, Resistivity, Adhesion, Morphology,and Diffusion”. J. Appl. Phys., 75(7) 1994, 3627-3631. Magnesium (Mg)has also been suggested as a doping material to improve the oxidationresistance of Cu.

There exists a need for semiconductor technology enabling the formationof Cu or Cu alloy metallization in interconnection patterns withimproved corrosion resistance while substantially reducing oreliminating Cu diffusion.

DISCLOSURE OF THE INVENTION

An object of the present invention is a method electroplating orelectroless plating Cu or Cu alloy metallization having high corrosionresistance without any substantial Cu diffusion.

Another object of the present invention is a semiconductor devicecomprising Cu or Cu alloy metallization exhibiting high corrosionresistance without any substantial Cu diffusion.

Additional objects, advantages and other features of the invention willbe set forth in the description which follows and in part will becomeapparent to those having ordinary skill in the art upon examination ofthe following or may be learned from the practice of the invention. Theobjects and advantages of the invention may be realized and obtained asparticularly pointed out in the appended claims.

According to the present invention, the foregoing and other objects areachieved in part by a method of manufacturing a semiconductor, whichmethod comprises: forming an opening in a dielectric layer; depositing ametal layer comprising an aluminum alloy or a magnesium alloy lining theopening; electroplating or electroless plating Cu or a Cu alloy on themetal layer to form a plated layer filling the opening; and annealing todiffuse aluminum or magnesium atoms from the metal layer through theplated layer, which Al or Mg atoms accumulate on the surface of theplated layer.

Another aspect of the present invention is a semiconductor device havingan interconnection pattern comprising: a dielectric layer having anopening therein; and a composite metal layer inlaid in the opening, thecomposite metal layer comprising: a metal layer comprising an aluminumor a magnesium alloy lining the opening; a plated layer comprisingelectroplated or electroless plated copper or a copper alloy on themetal layer filling the trench; and a layer of aluminum oxide ormagnesium oxide on and encapsulating the plated layer.

Additional objects and advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description, wherein embodiments of the invention are describedsimply by way of illustrating of the best mode contemplated in carryingout the invention. As will be realized, the invention is capable ofother and different embodiments, and its several details are capable ofmodifications in various obvious respects, all without departing fromthe invention. Accordingly, the drawings and description are to beregarded as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 illustrate sequential phases of a method in accordance with anembodiment of the present invention.

FIGS. 5-7 illustrate sequential phases of a method in accordance withanother embodiment of the present invention.

DESCRIPTION OF THE INVENTION

The present invention addresses and solves the corrosion problemsattendant upon electroplated or electroless plated Cu metallization in acost effective, simplified manner. In various embodiments of the presentinvention, the foregoing objective is achieved by initially depositing ametal layer comprising an Al or Mg alloy, and then electroplating orelectroless plating Cu or a Cu alloy thereon. Low temperature annealingis then conducted, during which Al or Mg from the underlying Al alloy orMg alloy layer diffuses through the plated Cu or Cu alloy, accumulatingat the surface thereof, because of its (i.e., Al or Mg) low solubilityin Cu, and forms a passivating or protective oxide coating on andsubstantially encapsulating the plated Cu or Cu alloy layer, and at theinterface between the underlying Al or Mg alloy layer and a dielectricoxide layer, as well as on the underlying layer. As used throughout thisapplication, the expression “Cu metallization” denotes electroplated orelectroless plated Cu or a Cu alloy.

The particular temperature and the thickness of the underlying Al alloyor Mg alloy layer can be optimized in a particular situation. Forexample, it has been found that an Al alloy or Mg alloy layer having athickness of about 50 Å to about 1500 Å is suitable in practicing thepresent invention. An annealing temperature of about 150° C. to 450° C.has been found effective in diffusing Mg or Al through a Cumetallization and to form an effective protective encapsulating oxide onthe exposed surface of the Cu metallization, and on the exposed surfaceof, and at the interface between, the Al or Mg alloy layer and thedielectric oxide layer. The time of annealing can be optimized in aparticular situation depending upon the dimensions of the Cumetallization, annealing temperature and particular Al or Mg alloy.

The embodiments of the present invention for producing protective oxideself-encapsulated Cu metallization are particularly applicable inconjunction with damascene techniques wherein an opening is formed in adielectric layer, such as a silicon oxide, e.g. silicon dioxide. Thepresent invention, however, is not limited to dielectric layerscomprising silicon oxide, but can be employed in the context of variousdielectric materials, such as low dielectric constant polymers.

Thus, in accordance with the present invention, Cu metallization havinga protected, self-encapsulated oxide layer is formed in a damasceneopening in a dielectric layer. The damascene opening can be a trench, inwhich case the Cu metallization forms an interconnection line, or avia/contact hole in which case the Cu metallization forms a via/contact.Double damascene techniques can be employed in which the openingcontains a first portion forming a trench and a second portion forming avia/contact hole in communication with the trench, in which case the Cumetallization comprises a first section filling the trench and formingan interconnection line and a second portion filling the hole andforming a contact/via with the interconnecting line electricalconnection. The present invention advantageously enables fillingopenings having high aspect ratios, e.g., greater than about 3:1 withimproved uniformity.

Embodiments of the present invention include depositing a diffusionbarrier layer prior to depositing the Al alloy or Mg alloy layer, foreven greater diffusion prevention. Such a diffusion barrier layer cancomprise any of a variety of metals, such as tantalum (Ta), Ta alloys, Wor W alloys, and titanium (Ti) or Ti alloys. The diffusion barrier layercan be formed at a thickness of about 50 Å to about 1,500 Å. Optionally,an adhesion promoting layer can be deposited prior to depositing thediffusion barrier layer. A suitable adhesion promoting layer comprisesTi and has a thickness of about 50 Å to about 1,500 Å. The adhesionpromoting layer as well as diffusion barrier layer can be deposited byany of various conventional deposition techniques, such as PVD or CVD.

In other embodiments of the present invention, a seed layer is depositedon the Al alloy or Mg alloy layer for enhanced nucleation and adhesionof the electroplated or electroless plated Cu or Cu alloy layer. Theseed layer can comprise an alloy of Cu and any of various alloyingelements such as Mg, Al, Zinc (Zn), Zirconium (Zr), tin (Sn), nickel(Ni), palladium (Pd), silver (Ag) or gold (Au). The seed layer can besputter deposited or deposited by CVD.

Embodiments of the present invention include electroless plating orelectroplating various Cu alloys, such as alloys of Cu with Mg, Zn, Zr,Sn, Ni, or Pd. After electroplating or electroless plating Cu or Cualloy on the Al alloy or Mg alloy layer, CMP is typically performed toprovide a planarized surface. Low temperature annealing is thenconducted to diffuse Al atoms or Mg atoms from the underlying Al alloyor Mg alloy layer through the Cu metallization and accumulate on thesurface thereof to form a passivating protective aluminum oxide (Al₂O₃)or magnesium oxide (MgO) self-encapsulating coating. Advantageously, theprotective encapsulating oxide coating prevents corrosion of the Cumetallization and prevents diffusion of Cu atoms from the Cumetallization through the dielectric layer into the silicon elements.Thermal annealing can be conducted in a hydrogen atmosphere, e.g., anatmosphere containing up to 100% hydrogen, e.g., 1% hydrogen or 5%hydrogen, or an atmosphere of pure ammonia (NH₃).

An embodiment of the present invention is schematically illustrated inFIGS. 1-4, wherein similar elements bear similar reference numerals.Adverting to FIG. 1, damascene openings are etched in a conventionalmanner in a dielectric layer 10, typically comprising silicon dioxide.The damascene openings include a trench 12 and a dual damascene openingcomprising via hole 13A in communication with trench 13B. As illustratedvia hole 13A communicates with an underlying interconnection line 11.However, the present invention is also applicable to a single damasceneopening comprising a via hole, a single damascene opening comprising acontact hole or a dual damascene opening comprising a contact hole incommunication with a trench.

With continued reference to FIG. 1, after formation of the damasceneopening or openings, a layer comprising an Al alloy or a Mg alloy 14,typically containing about 0.1 to about 90 atomic percent of Al or Mg,respectively, is deposited to line the damascene openings. The Al or Mgalloys can contain such alloying elements as Cu, Ta, W, silicon (Si) ornitrogen (N) . The Al alloy or Mg alloy can be deposited by a PVDtechnique, such as sputtering, or a CVD technique. Typically the Alalloy or Mg alloy layer is deposited to a thickness of about 50 Å toabout 1500 Å. As shown in FIG. 1, the Al alloy layer or Mg alloy layer14 lines the damascene openings as well as the upper surface ofdielectric layer 10.

Adverting to FIG. 2, a Cu or Cu alloy layer 20 is then electroplated orelectroless plated on the surface of the Al or Mg alloy layer 14.Suitable Cu alloys include alloys of Cu with any of various metals, suchas Mg, Sn, Zn, Pd, Au, Ag, Zr and Ni.

Subsequently, as shown in FIG. 3, CMP is performed to provide aplanarized upper surface 30, Cu metallization interconnection line 31 isformed in trench 12 (FIG. 1), while a dual damascene Cu metallizationstructure comprising via 32A connected to interconnection line 32B isformed via hole 13A and trench 13B (FIG. 1)

Adverting to FIG. 4, subsequent to planarization, thermal annealing isconducted at a relatively low temperature of about 150° C. to 450° C.,as in a hydrogen or ammonia ambient. During thermal annealing, Al atomsor Mg atoms from underlying layer 14 diffuse through the Cumetallization, accumulate on the surface thereof and oxidize to form aself-passivating, self-encapsulating oxide layer 40 on the exposedinterconnection line 31 and on the exposed dual damascene structurecomprising via 32A and interconnection line 32B. In addition, aself-passivating oxide layer 40 is formed on the exposed surface of, andat the interface between, underlying layer 14 and dielectric layer 10when employing an oxide dielectric layer. The self-encapsulating oxide40, typically has a thickness of about 20 Å to about 200 Å and preventscorrosion of the Cu metallization as well as diffusion of Cu throughdielectric layer 10 to active silicon devices.

Another embodiment of the present invention is schematically illustratedin FIGS. 5-7, wherein similar elements bear similar reference numerals.The embodiment schematically illustrated in FIGS. 5-7 is similar to theembodiment schematically illustrated in FIGS. 1-4, except that aninitial barrier layer 52 is deposited in the damascene openings indielectric layer 50 formed over conductive line 51. Barrier layer 52provides additional protection against diffusion of Cu atoms from the Cumetallization through dielectric layer 50. Suitable barrier layers caninclude Ti, W, Sn, Si, N, Pd, Ta, and alloys thereof. After depositionof the barrier layer 52, Al or Mg alloy layer 53 is deposited on barrierlayer 52 lining the damascene openings. Cu metallization 54 is thendeposited filling the damascene openings and extending above the uppersurface of substrate 50.

Adverting to FIG. 6, CMP is then conducted to form planarized uppersurface 60. The resulting Cu metallization comprises interconnectionline 61 and a dual damascene Cu metallization structure comprising via62A electrically connected to interconnection line 62B. Thermalannealing is then conducted, during which Al atoms or Mg atoms fromunderlying layer 53 diffuse through the Cu metallization, accumulate onthe exposed surface thereof, and react with oxygen to form aself-passivating Al oxide or Mg oxide layer 70 encapsulatinginterconnection 61 and dual damascene Cu metallization 62A, 62B.

Other embodiments of the present invention, include initially depositingan adhesion promoting layer prior to depositing the diffusion barrierlayer 52, as illustrated by reference numeral 55 in FIG. 5. Suchadhesion promoting layers can comprise materials such as chromium (Cr),Ta, vanadium (V), and molybdenum (Mo).

Other embodiments of the present invention include depositing a seedlayer on the Al alloy or Mg alloy layer to improve nucleation andadhesion of the Cu metallization, as illustrated by reference numeral 56in FIG. 5. Such seed layers can include various Cu alloys, such as a Cualloyed with Mg, Al, Zn, Zr, Sn, Ni, Pd, Ag or Au. The adhesionpromoting layer 55 and seed layer 56 are now shown in FIGS. 6 and 7 forillustrative clarity.

In accordance with the present invention, Cu metallization structuresare formed in an efficient, cost-effective manner. The use of Al alloysor Mg alloys avoids the difficulty in plating Cu directly on Al or Mg,since Al and Mg is easily dissolved in a plating solution. Theself-encapsulated Cu metallization formed in accordance with the presentinvention is particularly advantageous in forming inlaid Cumetallization interconnection patterns, particularly in various types ofsemiconductor devices having sub-micron features and high aspect ratioopenings.

In the previous descriptions, numerous specific details are set forth,such as specific materials, structures, chemicals, processes, etc., inorder to provide a better understanding of the present invention.However, the present invention can be practiced without resorting to thedetails specifically set forth. In other instances, well-knownprocessing structures have not been described in detail in order not tounnecessarily obscure the present invention.

Only the preferred embodiment of the invention and but a few examples ofits versatility are shown and described in the present disclosure. It isto be understood that the present invention is capable of use in variousother combinations and environments and is capable of changes ormodifications within the scope of the inventive concept as expressedherein.

What is claimed is:
 1. A semiconductor device having an interconnectionpattern comprising: a dielectric layer having an opening therein; and acomposite metal layer inlaid in the opening, the composite metal layercomprising: a metal layer comprising a magnesium alloy lining the entireopening; a plated layer, comprising an upper surface, comprisingelectroplated or electroless plated copper or a copper alloy on themetal layer filling the opening; and a layer of magnesium oxide, formed:(a) directly on the upper surface of and encapsulating the plated layer;and (b) directly on the entire surface of the metal layer lining theopening which is between the metal layer and the dielectric layer. 2.The semiconductor device according to claim 1, wherein the metal layercomprises an alloy containing about 0.1 to about 90 atomic percent Mg.